FIG. 1 illustrates a conventional six-pin package 10 containing an integrated circuit chip. There may be any number of pins extending from the package. It is common in certain types of circuits to allow the user to set an internal current by connecting a component, such as a resistor, to a specified pin of the package. FIG. 1 illustrates a current set resistor Rset connected to a control pin 12 of the package.
FIG. 2 illustrates one type of current setting circuit 14 internal to the chip, where the external resistor Rset sets a current internal to the chip. The user-selected current may be for setting timing, setting a frequency, setting a threshold, setting an output current, setting a bias, or any other use. The low voltage reference internal to the chip is identified as Vee, which may be ground.
In FIG. 2, lowering the value of Rset increases the internal current set (Iset) level. A proportional current, labeled A*Iset, is then used by the chip for any purpose.
A differential amplifier consists of transistors Q0-Q3. Transistors Q1 and Q0 are connected as a current mirror so that the currents through Q1 and Q0 are approximately equal. A fixed reference voltage Vref sets a current through Q1 and Q2. The sum of the currents through Q2 and Q3 equals the current drawn by the constant current source 16.
Feedback is used so that the current (Iset) through the resistor Rset causes the voltage drop across Rset to always be slightly lower than Vref to maintain equilibrium in the circuit. A lower value of Rset requires a greater Iset to create the required voltage drop for equilibrium.
As an example of the circuit's operation, if the voltage at pin 12 were initially much less than Vref, then less current flows through Q3, and the extra current generated by Q0 flows into the base of Q4 to increase the Iset current through Q4 and the resistor Rset. This increases the voltage drop across Rset until there is equilibrium, whereby Q3 is controlled by the voltage drop to allow only that excess current into the base of Q4 necessary to maintain the circuit at equilibrium. Since only a small variation in the Q3 base current causes a large variation in Iset current, the voltage drop across Rset is only slightly less than Vref.
A current mirror formed by Q5 and Q6 causes a proportional current (A*Iset) to flow through Q6. The proportion is typically determined by the relative emitter sizes of the transistors. The current through Q6 is typically many times that of the current through Q5. Other currents may also be generated by other current mirror bank transistors Qn.
During the use of the circuit of FIGS. 1 and 2, pin 12 may be unintentionally shorted to ground or the user may mistakenly connect a resistor to pin 12 that has too low a value. If pin 12 is shorted to ground, this will cause all current generated by Q0 to flow into the base of Q4 to create very high Iset and A*Iset currents. Such high currents may damage the transistors and other components on the chip. Further, if the A*Iset current is used to control circuits external to the package 10 of FIG. 1, such overcurrents may also damage such external circuits.